This application claims priority to Korean Patent Application No. 2001-46632 filed on Aug. 1, 2001.
1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of performing a write latency operation.
2. Description of Related Art
A semiconductor memory device such as a synchronous dynamic random access memory device (SDRAM) or a double data rate synchronous dynamic random access memory device (DDR SDRAM) supports a write latency operation, wherein data is written in the memory device after a predetermined clock cycle is lapsed from receiving a write command. For example, if write latency is xe2x80x9c1xe2x80x9d, data is written after one clock cycle is lapsed from receiving a write command, and if the write latency is xe2x80x9c3xe2x80x9d, data is written after three clock cycles are lapsed from receiving the write command.
When an apparatus includes a semiconductor memory device having fixed write latency, the efficiency of the command bus of the apparatus is decreased. There are semiconductor memory devices having a variable write latency, wherein a write latency value is varied with or without a column address strobe (CAS) latency. For example, when an apparatus has a relatively low operation frequency, i.e., CAS is less than 3, a burst stop can be used and a semiconductor memory device having a write latency to a fixed value will achieve high bus efficiency. On the other hand, when an apparatus has a relatively high operation frequency, i.e., CAS is greater than 2, the burst stop cannot be used and a semiconductor memory device having a write latency set to a variable value will achieve high bus efficiency.
Accordingly, a need exists for a semiconductor memory device that can set write latency to a fixed value or a variable value based on CAS latency to achieve high bus efficiency of an apparatus employing the semiconductor memory device.
It is an object of the present invention to provide a semiconductor memory device capable of improving command bus efficiency and method thereof.
According to an aspect of the present invention, a semiconductor memory device comprises an address shifting circuit for delaying an address by an n+m number of clock cycles in response to a clock signal, a control signal generating circuit for combining a column address strobe (CAS) latency of n-value and one of first and second operation signals to generate a control signal, wherein the first operation signal indicates that the n-value of the CAS latency is less than a predetermined value and write latency is fixed, wherein the second operation signal indicates that the n-value of the CAS latency is equal to or greater than the predetermined value and the write latency is variable, and a switching circuit for outputting the address delayed by the n+m number of clock cycles output from the address shifting circuit in response to the control signal.
According to another aspect of the present invneiton, a method is provided for controlling a write latency operation of a semiconductor memory device comprising the stesp of delaying an address by n+m clock cycles in response to a clock signal, generating a first control signal by combining a column address strobe (CAS) latency signal of n-value and a first operation signal, when the n-value of the CAS latency is less than a predetermined value and write latency is fixed, generating a second control signal by combining the column address strobe (CAS) latency of n-value and a second operation signal, when the n-value of the CAS latency is eqaul to or greater than the predetermined value and the write latency is variable, and outputting the address delayed by the n+m clock cycles in response to corresponding one of the first and second control signal.
According to another aspect of the present invneiton, a semiconductor memory device comprises an address shifting circuit for shifting an address by a predetermined number of clock cycles to generate a plurality of delayed addresses, in response to a clock signal, a control signal generating circuit for combining column address strobe (CAS) latency and one of first and second operation signals based on a value of the CAS latency to generate a control signal, and a switching circuit for selecting one of the delayed addresses output from the address shifting circuit in response to the control signal.
According to further aspect of the present invention, a method is provided for controlling a write latency operation of a semiconductor memory device comprising the steps of shifting an address by a predetermined number of clock cycles to generate a plurality of delayed addresses, in response to a clock signal, generating a control signal by combining column address strobe (CAS) latency and one of first and second operation signals based on a value of the CAS latency, and selecting one of the delayed addresses in response to the control signal.
These and other aspects, features, and advantages of the present invention will become apparent from the following detailed description of preferred embodiments, which is to be read in conjunction with the accompanying figures.